
// **************************************************************
// Copyright (c) 2021 Xidian University.
// File name     : slave_decode.v
// Module name   : 
// Created Date  : 2021-07-12 15:35:35
// Author        : Zhang-Jianyuan
// Email         : 1227850326@qq.com
// -------------------------------------------------------------------------
// Version       : 
// Last Modified : 2021-07-12 15:36:24
// Modified By   : 
// -------------------------------------------------------------------------
// 
// -------------------------------------------------------------------------
// HISTORY       : 
// Date         By  Comments
// ------------ --  ----------------------------------------------------------
// 
// 
// 
// **************************************************************
// 
// 
// 
// *******************
// TIMESCALE
// *******************
// 
// 
// 
// *******************
// INCLUDE
// *******************
// 
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
`include "top_define.v"
// 
// *******************
// INFORMATION
// *******************
// 
// 
// 
// *******************
// DEFINE(s)
// *******************
// 
// 
// 
// *******************
// DEFINE MODULE PORT
// *******************
// 
module np_slave_decode#(parameter SLAVE_NUM = 26)(
     input  wire         clk_sys                 
    ,input  wire         rst_n_sys               
    ,input  wire         np_sel_en               
    ,input  wire         np_wr
    ,input  wire         np_rd
    ,input  wire [31:0]  np_addr_in              
    ,output reg  [15:0]  np_addr_in_d2           
    ,output wire [SLAVE_NUM*2+1:0]  bus1_np_addr_ctrl
    ,output wire [SLAVE_NUM*2-1:0]  bus2_np_addr_ctrl
    ,output wire [SLAVE_NUM*2-1:0]  bus3_np_addr_ctrl
    ,output wire [SLAVE_NUM*2-1:0]  bus4_np_addr_ctrl
);
// *******************
// DEFINE LOCAL PARAMETER
// *******************
// 
// 
// *******************
// INNER SIGNAL DECLARATION
// *******************
// REGS
// 
reg bus1_me_tab_sel;
reg bus1_que_ist_cap_ctl_sel;
reg bus1_pars_phy_mac_pcs_sel;
reg bus2_me_tab_sel;
reg bus2_que_ist_cap_ctl_sel;
reg bus2_pars_phy_mac_pcs_sel;
reg bus3_me_tab_sel;
reg bus3_que_ist_cap_ctl_sel;
reg bus3_pars_phy_mac_pcs_sel;
reg bus4_me_tab_sel;
reg bus4_que_ist_cap_ctl_sel;
reg bus4_pars_phy_mac_pcs_sel;


reg bus1_me_tab_sel_en;
reg bus1_que_ist_cap_ctl_sel_en;
reg bus1_pars_phy_mac_pcs_sel_en;
reg bus2_me_tab_sel_en;
reg bus2_que_ist_cap_ctl_sel_en;
reg bus2_pars_phy_mac_pcs_sel_en;
reg bus3_me_tab_sel_en;
reg bus3_que_ist_cap_ctl_sel_en;
reg bus3_pars_phy_mac_pcs_sel_en;
reg bus4_me_tab_sel_en;
reg bus4_que_ist_cap_ctl_sel_en;
reg bus4_pars_phy_mac_pcs_sel_en;

reg [31:0]np_addr_in_d1;
reg np_wr_d1,np_wr_d2;//,np_wr_d3;
reg np_rd_d1,np_rd_d2;//,np_rd_d3;

reg bus1_np_reg_sel;
reg bus1_bv1_sel;
reg bus1_hash2_sel;
reg bus1_rbve1_3_sel;
reg bus1_rbve2_3_sel;
reg bus1_bv4_sel;
reg bus1_bv5_sel;
reg bus1_bv6_sel;
reg bus1_unicam7_sel;
reg bus1_mulcam8_sel;
reg bus1_action1_sel;
reg bus1_action3_sel;
reg bus1_action4_sel;
reg bus1_action5_sel;
reg bus1_action6_sel;
reg bus1_parameter3_sel;
reg bus1_parameter4_sel;
reg bus1_parameter5_sel;
reg bus1_parameter6_sel;
reg bus1_queue_threshold_sel;
reg bus1_tx_frame_cnt_sel;
reg bus1_rx_frame_cnt_sel;
reg bus1_node_pri_que_max_thr_sel;
reg bus1_node_pri_que_max_min_thr_sel;
reg bus1_insert_sel;
reg bus1_capture_sel;
reg bus1_flow_ctrl_sel;
reg bus1_token_rate_sel;
reg bus1_enqueue_frame_len_cnt_sel;
reg bus1_queue_info_sel;
reg bus1_parser_bv_sel;
reg bus1_parser_ram_sel;
reg bus1_deparser_sel;
reg bus1_field_select_sel;
reg bus1_phy_sel;
reg bus1_pcs_40G_sel;
reg bus1_pcs_10G_sel;
reg bus1_mac_sel;
reg bus2_np_reg_sel;
reg bus2_bv1_sel;
reg bus2_hash2_sel;
reg bus2_rbve1_3_sel;
reg bus2_rbve2_3_sel;
reg bus2_bv4_sel;
reg bus2_bv5_sel;
reg bus2_bv6_sel;
reg bus2_unicam7_sel;
reg bus2_mulcam8_sel;
reg bus2_action1_sel;
reg bus2_action3_sel;
reg bus2_action4_sel;
reg bus2_action5_sel;
reg bus2_action6_sel;
reg bus2_parameter3_sel;
reg bus2_parameter4_sel;
reg bus2_parameter5_sel;
reg bus2_parameter6_sel;
reg bus2_queue_threshold_sel;
reg bus2_tx_frame_cnt_sel;
reg bus2_rx_frame_cnt_sel;
reg bus2_node_pri_que_max_thr_sel;
reg bus2_node_pri_que_max_min_thr_sel;
reg bus2_insert_sel;
reg bus2_capture_sel;
reg bus2_flow_ctrl_sel;
reg bus2_token_rate_sel;
reg bus2_enqueue_frame_len_cnt_sel;
reg bus2_queue_info_sel;
reg bus2_parser_bv_sel;
reg bus2_parser_ram_sel;
reg bus2_deparser_sel;
reg bus2_field_select_sel;
reg bus2_phy_sel;
reg bus2_pcs_40G_sel;
reg bus2_pcs_10G_sel;
reg bus2_mac_sel;
reg bus3_np_reg_sel;
reg bus3_bv1_sel;
reg bus3_hash2_sel;
reg bus3_rbve1_3_sel;
reg bus3_rbve2_3_sel;
reg bus3_bv4_sel;
reg bus3_bv5_sel;
reg bus3_bv6_sel;
reg bus3_unicam7_sel;
reg bus3_mulcam8_sel;
reg bus3_action1_sel;
reg bus3_action3_sel;
reg bus3_action4_sel;
reg bus3_action5_sel;
reg bus3_action6_sel;
reg bus3_parameter3_sel;
reg bus3_parameter4_sel;
reg bus3_parameter5_sel;
reg bus3_parameter6_sel;
reg bus3_queue_threshold_sel;
reg bus3_tx_frame_cnt_sel;
reg bus3_rx_frame_cnt_sel;
reg bus3_node_pri_que_max_thr_sel;
reg bus3_node_pri_que_max_min_thr_sel;
reg bus3_insert_sel;
reg bus3_capture_sel;
reg bus3_flow_ctrl_sel;
reg bus3_token_rate_sel;
reg bus3_enqueue_frame_len_cnt_sel;
reg bus3_queue_info_sel;
reg bus3_parser_bv_sel;
reg bus3_parser_ram_sel;
reg bus3_deparser_sel;
reg bus3_field_select_sel;
reg bus3_phy_sel;
reg bus3_pcs_40G_sel;
reg bus3_pcs_10G_sel;
reg bus3_mac_sel;
reg bus4_np_reg_sel;
reg bus4_bv1_sel;
reg bus4_hash2_sel;
reg bus4_rbve1_3_sel;
reg bus4_rbve2_3_sel;
reg bus4_bv4_sel;
reg bus4_bv5_sel;
reg bus4_bv6_sel;
reg bus4_unicam7_sel;
reg bus4_mulcam8_sel;
reg bus4_action1_sel;
reg bus4_action3_sel;
reg bus4_action4_sel;
reg bus4_action5_sel;
reg bus4_action6_sel;
reg bus4_parameter3_sel;
reg bus4_parameter4_sel;
reg bus4_parameter5_sel;
reg bus4_parameter6_sel;
reg bus4_queue_threshold_sel;
reg bus4_tx_frame_cnt_sel;
reg bus4_rx_frame_cnt_sel;
reg bus4_node_pri_que_max_thr_sel;
reg bus4_node_pri_que_max_min_thr_sel;
reg bus4_insert_sel;
reg bus4_capture_sel;
reg bus4_flow_ctrl_sel;
reg bus4_token_rate_sel;
reg bus4_enqueue_frame_len_cnt_sel;
reg bus4_queue_info_sel;
reg bus4_parser_bv_sel;
reg bus4_parser_ram_sel;
reg bus4_deparser_sel;
reg bus4_field_select_sel;
reg bus4_phy_sel;
reg bus4_pcs_40G_sel;
reg bus4_pcs_10G_sel;
reg bus4_mac_sel;


// 
// WIRES
// 
// 
// *******************
// INSTANTCE MODULE
// *******************
// 
// 
// 
// *******************
// MAIN CORE
// *******************
// 
always @(posedge clk_sys or negedge rst_n_sys) begin
    if(~rst_n_sys)begin
        np_addr_in_d1 <= 'h0;
        np_addr_in_d2 <= 'h0;
    end else begin
        np_addr_in_d1 <= np_addr_in;
        np_addr_in_d2 <= np_addr_in_d1[17:2];
    end
end

always @(posedge clk_sys or negedge rst_n_sys) begin
    if(~rst_n_sys)begin
        np_wr_d1 <= 'h0;
        np_wr_d2 <= 'h0;
        // np_wr_d3 <= 'h0;
    end else begin
        np_wr_d1 <= np_wr;
        np_wr_d2 <= np_wr_d1;
        // np_wr_d3 <= np_wr_d2;
    end
end
always @(posedge clk_sys or negedge rst_n_sys) begin
    if(~rst_n_sys)begin
        np_rd_d1 <= 'h0;
        np_rd_d2 <= 'h0;
        // np_rd_d3 <= 'h0;
    end else begin
        np_rd_d1 <= np_rd;
        np_rd_d2 <= np_rd_d1;
        // np_rd_d3 <= np_rd_d2;
    end
end

always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b0000)
        bus1_me_tab_sel = 1'b1;
    else
        bus1_me_tab_sel = 1'b0;
end
always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b0001)
        bus1_que_ist_cap_ctl_sel = 1'b1;
    else
        bus1_que_ist_cap_ctl_sel = 1'b0;
end
always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b0010)
        bus1_pars_phy_mac_pcs_sel = 1'b1;
    else
        bus1_pars_phy_mac_pcs_sel = 1'b0;
end

always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b0100)
        bus2_me_tab_sel = 1'b1;
    else
        bus2_me_tab_sel = 1'b0;
end
always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b0101)
        bus2_que_ist_cap_ctl_sel = 1'b1;
    else
        bus2_que_ist_cap_ctl_sel = 1'b0;
end
always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b0110)
        bus2_pars_phy_mac_pcs_sel = 1'b1;
    else
        bus2_pars_phy_mac_pcs_sel = 1'b0;
end

always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b1000)
        bus3_me_tab_sel = 1'b1;
    else
        bus3_me_tab_sel = 1'b0;
end
always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b1001)
        bus3_que_ist_cap_ctl_sel = 1'b1;
    else
        bus3_que_ist_cap_ctl_sel = 1'b0;
end
always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b1010)
        bus3_pars_phy_mac_pcs_sel = 1'b1;
    else
        bus3_pars_phy_mac_pcs_sel = 1'b0;
end

always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b1100)
        bus4_me_tab_sel = 1'b1;
    else
        bus4_me_tab_sel = 1'b0;
end
always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b1101)
        bus4_que_ist_cap_ctl_sel = 1'b1;
    else
        bus4_que_ist_cap_ctl_sel = 1'b0;
end
always@(*)begin
    if(np_sel_en&&np_addr_in[27:24]==4'b1110)
        bus4_pars_phy_mac_pcs_sel = 1'b1;
    else
        bus4_pars_phy_mac_pcs_sel = 1'b0;
end

always @(posedge clk_sys or negedge rst_n_sys) begin
    if(~rst_n_sys)begin
        bus1_me_tab_sel_en              <= 'h0;
        bus1_que_ist_cap_ctl_sel_en     <= 'h0;
        bus1_pars_phy_mac_pcs_sel_en    <= 'h0;
        bus2_me_tab_sel_en              <= 'h0;
        bus2_que_ist_cap_ctl_sel_en     <= 'h0;
        bus2_pars_phy_mac_pcs_sel_en    <= 'h0;
        bus3_me_tab_sel_en              <= 'h0;
        bus3_que_ist_cap_ctl_sel_en     <= 'h0;
        bus3_pars_phy_mac_pcs_sel_en    <= 'h0;
        bus4_me_tab_sel_en              <= 'h0;
        bus4_que_ist_cap_ctl_sel_en     <= 'h0;
        bus4_pars_phy_mac_pcs_sel_en    <= 'h0;
    end else begin
        bus1_me_tab_sel_en              <=  bus1_me_tab_sel             ;
        bus1_que_ist_cap_ctl_sel_en     <=  bus1_que_ist_cap_ctl_sel    ;
        bus1_pars_phy_mac_pcs_sel_en    <=  bus1_pars_phy_mac_pcs_sel   ;
        bus2_me_tab_sel_en              <=  bus2_me_tab_sel             ;
        bus2_que_ist_cap_ctl_sel_en     <=  bus2_que_ist_cap_ctl_sel    ;
        bus2_pars_phy_mac_pcs_sel_en    <=  bus2_pars_phy_mac_pcs_sel   ;  
        bus3_me_tab_sel_en              <=  bus3_me_tab_sel             ;
        bus3_que_ist_cap_ctl_sel_en     <=  bus3_que_ist_cap_ctl_sel    ;
        bus3_pars_phy_mac_pcs_sel_en    <=  bus3_pars_phy_mac_pcs_sel   ;
        bus4_me_tab_sel_en              <=  bus4_me_tab_sel             ;
        bus4_que_ist_cap_ctl_sel_en     <=  bus4_que_ist_cap_ctl_sel    ;
        bus4_pars_phy_mac_pcs_sel_en    <=  bus4_pars_phy_mac_pcs_sel   ;
    end
end



always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:20]==4'b0000))
        bus1_np_reg_sel = 1'b1;
    else
        bus1_np_reg_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b000100))
        bus1_bv1_sel = 1'b1;
    else
        bus1_bv1_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus1_hash2_sel = 1'b1;
    else
        bus1_hash2_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && ({np_addr_in_d1[23:18],np_addr_in_d1[11]}==7'b0011000))
        bus1_rbve1_3_sel = 1'b1;
    else
        bus1_rbve1_3_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && ({np_addr_in_d1[23:18],np_addr_in_d1[11]}==7'b0011001))
        bus1_rbve2_3_sel = 1'b1;
    else
        bus1_rbve2_3_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus1_bv4_sel = 1'b1;
    else
        bus1_bv4_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010100))
        bus1_bv5_sel = 1'b1;
    else
        bus1_bv5_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus1_bv6_sel = 1'b1;
    else
        bus1_bv6_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011100))
        bus1_unicam7_sel = 1'b1;
    else
        bus1_unicam7_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b100000))
        bus1_mulcam8_sel = 1'b1;
    else
        bus1_mulcam8_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b000101))
        bus1_action1_sel = 1'b1;
    else
        bus1_action1_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001101))
        bus1_action3_sel = 1'b1;
    else
        bus1_action3_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010001))
        bus1_action4_sel = 1'b1;
    else
        bus1_action4_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010101))
        bus1_action5_sel = 1'b1;
    else
        bus1_action5_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011001))
        bus1_action6_sel = 1'b1;
    else
        bus1_action6_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001110))
        bus1_parameter3_sel = 1'b1;
    else
        bus1_parameter3_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010010))
        bus1_parameter4_sel = 1'b1;
    else
        bus1_parameter4_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010110))
        bus1_parameter5_sel = 1'b1;
    else
        bus1_parameter5_sel = 1'b0;
end

always @(*) begin
    if(bus1_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011010))
        bus1_parameter6_sel = 1'b1;
    else
        bus1_parameter6_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000000))
        bus1_queue_threshold_sel = 1'b1;
    else
        bus1_queue_threshold_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000001))
        bus1_tx_frame_cnt_sel = 1'b1;
    else
        bus1_tx_frame_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000010))
        bus1_rx_frame_cnt_sel = 1'b1;
    else
        bus1_rx_frame_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000011))
        bus1_node_pri_que_max_thr_sel = 1'b1;
    else
        bus1_node_pri_que_max_thr_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000100))
        bus1_node_pri_que_max_min_thr_sel = 1'b1;
    else
        bus1_node_pri_que_max_min_thr_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus1_insert_sel = 1'b1;
    else
        bus1_insert_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus1_capture_sel = 1'b1;
    else
        bus1_capture_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus1_flow_ctrl_sel = 1'b1;
    else
        bus1_flow_ctrl_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011001))
        bus1_token_rate_sel = 1'b1;
    else
        bus1_token_rate_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011010))
        bus1_enqueue_frame_len_cnt_sel = 1'b1;
    else
        bus1_enqueue_frame_len_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus1_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011011))
        bus1_queue_info_sel = 1'b1;
    else
        bus1_queue_info_sel = 1'b0;
end

always @(*) begin
    if(bus1_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000000))
        bus1_parser_bv_sel = 1'b1;
    else
        bus1_parser_bv_sel = 1'b0;
end

always @(*) begin
    if(bus1_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000001))
        bus1_parser_ram_sel = 1'b1;
    else
        bus1_parser_ram_sel = 1'b0;
end

always @(*) begin
    if(bus1_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000010))
        bus1_deparser_sel = 1'b1;
    else
        bus1_deparser_sel = 1'b0;
end

always @(*) begin
    if(bus1_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000011))
        bus1_field_select_sel = 1'b1;
    else
        bus1_field_select_sel = 1'b0;
end

always @(*) begin
    if(bus1_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus1_phy_sel = 1'b1;
    else
        bus1_phy_sel = 1'b0;
end

always @(*) begin
    if(bus1_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus1_pcs_40G_sel = 1'b1;
    else
        bus1_pcs_40G_sel = 1'b0;
end

always @(*) begin
    if(bus1_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b100000))
        bus1_pcs_10G_sel = 1'b1;
    else
        bus1_pcs_10G_sel = 1'b0;
end

always @(*) begin
    if(bus1_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus1_mac_sel = 1'b1;
    else
        bus1_mac_sel = 1'b0;
end





always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:20]==4'b0000))
        bus2_np_reg_sel = 1'b1;
    else
        bus2_np_reg_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b000100))
        bus2_bv1_sel = 1'b1;
    else
        bus2_bv1_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus2_hash2_sel = 1'b1;
    else
        bus2_hash2_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && ({np_addr_in_d1[23:18],np_addr_in_d1[11]}==7'b0011000))
        bus2_rbve1_3_sel = 1'b1;
    else
        bus2_rbve1_3_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && ({np_addr_in_d1[23:18],np_addr_in_d1[11]}==7'b0011001))
        bus2_rbve2_3_sel = 1'b1;
    else
        bus2_rbve2_3_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus2_bv4_sel = 1'b1;
    else
        bus2_bv4_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010100))
        bus2_bv5_sel = 1'b1;
    else
        bus2_bv5_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus2_bv6_sel = 1'b1;
    else
        bus2_bv6_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011100))
        bus2_unicam7_sel = 1'b1;
    else
        bus2_unicam7_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b100000))
        bus2_mulcam8_sel = 1'b1;
    else
        bus2_mulcam8_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b000101))
        bus2_action1_sel = 1'b1;
    else
        bus2_action1_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001101))
        bus2_action3_sel = 1'b1;
    else
        bus2_action3_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010001))
        bus2_action4_sel = 1'b1;
    else
        bus2_action4_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010101))
        bus2_action5_sel = 1'b1;
    else
        bus2_action5_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011001))
        bus2_action6_sel = 1'b1;
    else
        bus2_action6_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001110))
        bus2_parameter3_sel = 1'b1;
    else
        bus2_parameter3_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010010))
        bus2_parameter4_sel = 1'b1;
    else
        bus2_parameter4_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010110))
        bus2_parameter5_sel = 1'b1;
    else
        bus2_parameter5_sel = 1'b0;
end

always @(*) begin
    if(bus2_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011010))
        bus2_parameter6_sel = 1'b1;
    else
        bus2_parameter6_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000000))
        bus2_queue_threshold_sel = 1'b1;
    else
        bus2_queue_threshold_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000001))
        bus2_tx_frame_cnt_sel = 1'b1;
    else
        bus2_tx_frame_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000010))
        bus2_rx_frame_cnt_sel = 1'b1;
    else
        bus2_rx_frame_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000011))
        bus2_node_pri_que_max_thr_sel = 1'b1;
    else
        bus2_node_pri_que_max_thr_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000100))
        bus2_node_pri_que_max_min_thr_sel = 1'b1;
    else
        bus2_node_pri_que_max_min_thr_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus2_insert_sel = 1'b1;
    else
        bus2_insert_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus2_capture_sel = 1'b1;
    else
        bus2_capture_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus2_flow_ctrl_sel = 1'b1;
    else
        bus2_flow_ctrl_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011001))
        bus2_token_rate_sel = 1'b1;
    else
        bus2_token_rate_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011010))
        bus2_enqueue_frame_len_cnt_sel = 1'b1;
    else
        bus2_enqueue_frame_len_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus2_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011011))
        bus2_queue_info_sel = 1'b1;
    else
        bus2_queue_info_sel = 1'b0;
end

always @(*) begin
    if(bus2_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000000))
        bus2_parser_bv_sel = 1'b1;
    else
        bus2_parser_bv_sel = 1'b0;
end

always @(*) begin
    if(bus2_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000001))
        bus2_parser_ram_sel = 1'b1;
    else
        bus2_parser_ram_sel = 1'b0;
end

always @(*) begin
    if(bus2_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000010))
        bus2_deparser_sel = 1'b1;
    else
        bus2_deparser_sel = 1'b0;
end

always @(*) begin
    if(bus2_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000011))
        bus2_field_select_sel = 1'b1;
    else
        bus2_field_select_sel = 1'b0;
end

always @(*) begin
    if(bus2_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus2_phy_sel = 1'b1;
    else
        bus2_phy_sel = 1'b0;
end

always @(*) begin
    if(bus2_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus2_pcs_40G_sel = 1'b1;
    else
        bus2_pcs_40G_sel = 1'b0;
end

always @(*) begin
    if(bus2_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b100000))
        bus2_pcs_10G_sel = 1'b1;
    else
        bus2_pcs_10G_sel = 1'b0;
end

always @(*) begin
    if(bus2_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus2_mac_sel = 1'b1;
    else
        bus2_mac_sel = 1'b0;
end





always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:20]==4'b0000))
        bus3_np_reg_sel = 1'b1;
    else
        bus3_np_reg_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b000100))
        bus3_bv1_sel = 1'b1;
    else
        bus3_bv1_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus3_hash2_sel = 1'b1;
    else
        bus3_hash2_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && ({np_addr_in_d1[23:18],np_addr_in_d1[11]}==7'b0011000))
        bus3_rbve1_3_sel = 1'b1;
    else
        bus3_rbve1_3_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && ({np_addr_in_d1[23:18],np_addr_in_d1[11]}==7'b0011001))
        bus3_rbve2_3_sel = 1'b1;
    else
        bus3_rbve2_3_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus3_bv4_sel = 1'b1;
    else
        bus3_bv4_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010100))
        bus3_bv5_sel = 1'b1;
    else
        bus3_bv5_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus3_bv6_sel = 1'b1;
    else
        bus3_bv6_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011100))
        bus3_unicam7_sel = 1'b1;
    else
        bus3_unicam7_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b100000))
        bus3_mulcam8_sel = 1'b1;
    else
        bus3_mulcam8_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b000101))
        bus3_action1_sel = 1'b1;
    else
        bus3_action1_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001101))
        bus3_action3_sel = 1'b1;
    else
        bus3_action3_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010001))
        bus3_action4_sel = 1'b1;
    else
        bus3_action4_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010101))
        bus3_action5_sel = 1'b1;
    else
        bus3_action5_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011001))
        bus3_action6_sel = 1'b1;
    else
        bus3_action6_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001110))
        bus3_parameter3_sel = 1'b1;
    else
        bus3_parameter3_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010010))
        bus3_parameter4_sel = 1'b1;
    else
        bus3_parameter4_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010110))
        bus3_parameter5_sel = 1'b1;
    else
        bus3_parameter5_sel = 1'b0;
end

always @(*) begin
    if(bus3_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011010))
        bus3_parameter6_sel = 1'b1;
    else
        bus3_parameter6_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000000))
        bus3_queue_threshold_sel = 1'b1;
    else
        bus3_queue_threshold_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000001))
        bus3_tx_frame_cnt_sel = 1'b1;
    else
        bus3_tx_frame_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000010))
        bus3_rx_frame_cnt_sel = 1'b1;
    else
        bus3_rx_frame_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000011))
        bus3_node_pri_que_max_thr_sel = 1'b1;
    else
        bus3_node_pri_que_max_thr_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000100))
        bus3_node_pri_que_max_min_thr_sel = 1'b1;
    else
        bus3_node_pri_que_max_min_thr_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus3_insert_sel = 1'b1;
    else
        bus3_insert_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus3_capture_sel = 1'b1;
    else
        bus3_capture_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus3_flow_ctrl_sel = 1'b1;
    else
        bus3_flow_ctrl_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011001))
        bus3_token_rate_sel = 1'b1;
    else
        bus3_token_rate_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011010))
        bus3_enqueue_frame_len_cnt_sel = 1'b1;
    else
        bus3_enqueue_frame_len_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus3_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011011))
        bus3_queue_info_sel = 1'b1;
    else
        bus3_queue_info_sel = 1'b0;
end

always @(*) begin
    if(bus3_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000000))
        bus3_parser_bv_sel = 1'b1;
    else
        bus3_parser_bv_sel = 1'b0;
end

always @(*) begin
    if(bus3_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000001))
        bus3_parser_ram_sel = 1'b1;
    else
        bus3_parser_ram_sel = 1'b0;
end

always @(*) begin
    if(bus3_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000010))
        bus3_deparser_sel = 1'b1;
    else
        bus3_deparser_sel = 1'b0;
end

always @(*) begin
    if(bus3_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000011))
        bus3_field_select_sel = 1'b1;
    else
        bus3_field_select_sel = 1'b0;
end

always @(*) begin
    if(bus3_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus3_phy_sel = 1'b1;
    else
        bus3_phy_sel = 1'b0;
end

always @(*) begin
    if(bus3_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus3_pcs_40G_sel = 1'b1;
    else
        bus3_pcs_40G_sel = 1'b0;
end

always @(*) begin
    if(bus3_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b100000))
        bus3_pcs_10G_sel = 1'b1;
    else
        bus3_pcs_10G_sel = 1'b0;
end

always @(*) begin
    if(bus3_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus3_mac_sel = 1'b1;
    else
        bus3_mac_sel = 1'b0;
end





always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:20]==4'b0000))
        bus4_np_reg_sel = 1'b1;
    else
        bus4_np_reg_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b000100))
        bus4_bv1_sel = 1'b1;
    else
        bus4_bv1_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus4_hash2_sel = 1'b1;
    else
        bus4_hash2_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && ({np_addr_in_d1[23:18],np_addr_in_d1[11]}==7'b0011000))
        bus4_rbve1_3_sel = 1'b1;
    else
        bus4_rbve1_3_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && ({np_addr_in_d1[23:18],np_addr_in_d1[11]}==7'b0011001))
        bus4_rbve2_3_sel = 1'b1;
    else
        bus4_rbve2_3_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus4_bv4_sel = 1'b1;
    else
        bus4_bv4_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010100))
        bus4_bv5_sel = 1'b1;
    else
        bus4_bv5_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus4_bv6_sel = 1'b1;
    else
        bus4_bv6_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011100))
        bus4_unicam7_sel = 1'b1;
    else
        bus4_unicam7_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b100000))
        bus4_mulcam8_sel = 1'b1;
    else
        bus4_mulcam8_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b000101))
        bus4_action1_sel = 1'b1;
    else
        bus4_action1_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001101))
        bus4_action3_sel = 1'b1;
    else
        bus4_action3_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010001))
        bus4_action4_sel = 1'b1;
    else
        bus4_action4_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010101))
        bus4_action5_sel = 1'b1;
    else
        bus4_action5_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011001))
        bus4_action6_sel = 1'b1;
    else
        bus4_action6_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b001110))
        bus4_parameter3_sel = 1'b1;
    else
        bus4_parameter3_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010010))
        bus4_parameter4_sel = 1'b1;
    else
        bus4_parameter4_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b010110))
        bus4_parameter5_sel = 1'b1;
    else
        bus4_parameter5_sel = 1'b0;
end

always @(*) begin
    if(bus4_me_tab_sel_en && (np_addr_in_d1[23:18]==6'b011010))
        bus4_parameter6_sel = 1'b1;
    else
        bus4_parameter6_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000000))
        bus4_queue_threshold_sel = 1'b1;
    else
        bus4_queue_threshold_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000001))
        bus4_tx_frame_cnt_sel = 1'b1;
    else
        bus4_tx_frame_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000010))
        bus4_rx_frame_cnt_sel = 1'b1;
    else
        bus4_rx_frame_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000011))
        bus4_node_pri_que_max_thr_sel = 1'b1;
    else
        bus4_node_pri_que_max_thr_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b000100))
        bus4_node_pri_que_max_min_thr_sel = 1'b1;
    else
        bus4_node_pri_que_max_min_thr_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus4_insert_sel = 1'b1;
    else
        bus4_insert_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus4_capture_sel = 1'b1;
    else
        bus4_capture_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus4_flow_ctrl_sel = 1'b1;
    else
        bus4_flow_ctrl_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011001))
        bus4_token_rate_sel = 1'b1;
    else
        bus4_token_rate_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011010))
        bus4_enqueue_frame_len_cnt_sel = 1'b1;
    else
        bus4_enqueue_frame_len_cnt_sel = 1'b0;
end

always @(*) begin
    if(bus4_que_ist_cap_ctl_sel_en && (np_addr_in_d1[23:18]==6'b011011))
        bus4_queue_info_sel = 1'b1;
    else
        bus4_queue_info_sel = 1'b0;
end

always @(*) begin
    if(bus4_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000000))
        bus4_parser_bv_sel = 1'b1;
    else
        bus4_parser_bv_sel = 1'b0;
end

always @(*) begin
    if(bus4_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000001))
        bus4_parser_ram_sel = 1'b1;
    else
        bus4_parser_ram_sel = 1'b0;
end

always @(*) begin
    if(bus4_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000010))
        bus4_deparser_sel = 1'b1;
    else
        bus4_deparser_sel = 1'b0;
end

always @(*) begin
    if(bus4_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b000011))
        bus4_field_select_sel = 1'b1;
    else
        bus4_field_select_sel = 1'b0;
end

always @(*) begin
    if(bus4_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b001000))
        bus4_phy_sel = 1'b1;
    else
        bus4_phy_sel = 1'b0;
end

always @(*) begin
    if(bus4_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b010000))
        bus4_pcs_40G_sel = 1'b1;
    else
        bus4_pcs_40G_sel = 1'b0;
end

always @(*) begin
    if(bus4_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b100000))
        bus4_pcs_10G_sel = 1'b1;
    else
        bus4_pcs_10G_sel = 1'b0;
end

always @(*) begin
    if(bus4_pars_phy_mac_pcs_sel_en && (np_addr_in_d1[23:18]==6'b011000))
        bus4_mac_sel = 1'b1;
    else
        bus4_mac_sel = 1'b0;
end
wire [SLAVE_NUM:0]bus1_sel_ctrl;
assign bus1_sel_ctrl =  {bus1_np_reg_sel                    //37            // 26   // 22   // 20   // 14
                        ,bus1_bv1_sel                       //36            // 25   // 21   // 19   // 13
                        ,bus1_hash2_sel                     //35            // 24   // 20   // 18   // 12
                        ,bus1_rbve1_3_sel                   //34            // 23   // 19   // 17   // 11
                        ,bus1_rbve2_3_sel                   //33            // 22   // 18   // 16   // 10
                        ,bus1_bv4_sel                       //32            // 21   // 17   // 15   // 9
                        ,bus1_bv5_sel                       //31            // 20   // 16   // 14   // 8
                        ,bus1_bv6_sel                       //30            // 19   // 15   // 13   // 7
                        ,bus1_unicam7_sel                   //29            // 18   // 14   // 12   // 6
                        ,bus1_mulcam8_sel                   //28            // 17   // 13   // 11   // 5
                        ,bus1_action1_sel                   //27            // 16   // 12   // 10   // 4
                        // ,bus1_action3_sel                   //26
                        ,bus1_action4_sel                   //25            // 15   // 11   // 9    // 3
                        ,bus1_action5_sel                   //24            // 14   // 10   // 8    // 2
                        ,bus1_action6_sel                   //23            // 13   // 9    // 7    // 1
                        // ,bus1_parameter3_sel                //22
                        // ,bus1_parameter4_sel                //21
                        // ,bus1_parameter5_sel                //20
                        // ,bus1_parameter6_sel                //19
                        ,bus1_queue_threshold_sel           //18            // 12   
                        ,bus1_tx_frame_cnt_sel              //17            // 11   // 8    // 6
                        ,bus1_rx_frame_cnt_sel              //16            // 10   // 7    // 5
                        ,bus1_node_pri_que_max_thr_sel      //15            // 9    // 6    // 4
                        ,bus1_node_pri_que_max_min_thr_sel  //14            // 8    // 5    // 3
                        ,bus1_insert_sel                    //13            // 7    // 4    
                        ,bus1_capture_sel                   //12            // 6    // 3    
                        // ,bus1_flow_ctrl_sel                 //11         
                        ,bus1_token_rate_sel                //10            // 5    // 2    // 2
                        ,bus1_enqueue_frame_len_cnt_sel     // 9            // 4    // 1    // 1
                        // ,bus1_queue_info_sel                // 8         
                        // ,bus1_parser_bv_sel                 // 7
                        // ,bus1_parser_ram_sel                // 6
                        // ,bus1_deparser_sel                  // 5
                        ,bus1_field_select_sel              // 4            // 3    // 0    // 0    // 0
                        // ,bus1_phy_sel                       // 3                 
                        ,bus1_pcs_40G_sel                   // 2            // 2        
                        ,bus1_pcs_10G_sel                   // 1            // 1        
                        ,bus1_mac_sel};                     // 0            // 0        
wire [SLAVE_NUM-1:0]bus2_sel_ctrl;
assign bus2_sel_ctrl =  {bus2_np_reg_sel
                        ,bus2_bv1_sel
                        ,bus2_hash2_sel
                        ,bus2_rbve1_3_sel
                        ,bus2_rbve2_3_sel
                        ,bus2_bv4_sel
                        ,bus2_bv5_sel
                        ,bus2_bv6_sel
                        ,bus2_unicam7_sel
                        ,bus2_mulcam8_sel
                        ,bus2_action1_sel
                        // ,bus2_action3_sel
                        ,bus2_action4_sel
                        ,bus2_action5_sel
                        ,bus2_action6_sel
                        // ,bus2_parameter3_sel
                        // ,bus2_parameter4_sel
                        // ,bus2_parameter5_sel
                        // ,bus2_parameter6_sel
                        // ,bus2_queue_threshold_sel
                        ,bus2_tx_frame_cnt_sel
                        ,bus2_rx_frame_cnt_sel
                        ,bus2_node_pri_que_max_thr_sel
                        ,bus2_node_pri_que_max_min_thr_sel
                        ,bus2_insert_sel
                        ,bus2_capture_sel
                        // ,bus2_flow_ctrl_sel
                        ,bus2_token_rate_sel
                        ,bus2_enqueue_frame_len_cnt_sel
                        // ,bus2_queue_info_sel
                        // ,bus2_parser_bv_sel
                        // ,bus2_parser_ram_sel
                        // ,bus2_deparser_sel
                        ,bus2_field_select_sel
                        // ,bus2_phy_sel
                        ,bus2_pcs_40G_sel
                        ,bus2_pcs_10G_sel
                        ,bus2_mac_sel};

wire [SLAVE_NUM-1:0]bus3_sel_ctrl;
assign bus3_sel_ctrl =  {bus3_np_reg_sel
                        ,bus3_bv1_sel
                        ,bus3_hash2_sel
                        ,bus3_rbve1_3_sel
                        ,bus3_rbve2_3_sel
                        ,bus3_bv4_sel
                        ,bus3_bv5_sel
                        ,bus3_bv6_sel
                        ,bus3_unicam7_sel
                        ,bus3_mulcam8_sel
                        ,bus3_action1_sel
                        // ,bus3_action3_sel
                        ,bus3_action4_sel
                        ,bus3_action5_sel
                        ,bus3_action6_sel
                        // ,bus3_parameter3_sel
                        // ,bus3_parameter4_sel
                        // ,bus3_parameter5_sel
                        // ,bus3_parameter6_sel
                        // ,bus3_queue_threshold_sel
                        ,bus3_tx_frame_cnt_sel
                        ,bus3_rx_frame_cnt_sel
                        ,bus3_node_pri_que_max_thr_sel
                        ,bus3_node_pri_que_max_min_thr_sel
                        ,bus3_insert_sel
                        ,bus3_capture_sel
                        // ,bus3_flow_ctrl_sel
                        ,bus3_token_rate_sel
                        ,bus3_enqueue_frame_len_cnt_sel
                        // ,bus3_queue_info_sel
                        // ,bus3_parser_bv_sel
                        // ,bus3_parser_ram_sel
                        // ,bus3_deparser_sel
                        ,bus3_field_select_sel
                        // ,bus3_phy_sel
                        ,bus3_pcs_40G_sel
                        ,bus3_pcs_10G_sel
                        ,bus3_mac_sel};

wire [SLAVE_NUM-1:0]bus4_sel_ctrl;
assign bus4_sel_ctrl =  {bus4_np_reg_sel
                        ,bus4_bv1_sel
                        ,bus4_hash2_sel
                        ,bus4_rbve1_3_sel
                        ,bus4_rbve2_3_sel
                        ,bus4_bv4_sel
                        ,bus4_bv5_sel
                        ,bus4_bv6_sel
                        ,bus4_unicam7_sel
                        ,bus4_mulcam8_sel
                        ,bus4_action1_sel
                        // ,bus4_action3_sel
                        ,bus4_action4_sel
                        ,bus4_action5_sel
                        ,bus4_action6_sel
                        // ,bus4_parameter3_sel
                        // ,bus4_parameter4_sel
                        // ,bus4_parameter5_sel
                        // ,bus4_parameter6_sel
                        // ,bus4_queue_threshold_sel
                        ,bus4_tx_frame_cnt_sel
                        ,bus4_rx_frame_cnt_sel
                        ,bus4_node_pri_que_max_thr_sel
                        ,bus4_node_pri_que_max_min_thr_sel
                        ,bus4_insert_sel
                        ,bus4_capture_sel
                        // ,bus4_flow_ctrl_sel
                        ,bus4_token_rate_sel
                        ,bus4_enqueue_frame_len_cnt_sel
                        // ,bus4_queue_info_sel
                        // ,bus4_parser_bv_sel
                        // ,bus4_parser_ram_sel
                        // ,bus4_deparser_sel
                        ,bus4_field_select_sel
                        // ,bus4_phy_sel
                        ,bus4_pcs_40G_sel
                        ,bus4_pcs_10G_sel
                        ,bus4_mac_sel};


reg [SLAVE_NUM  :0]bus1_sel_ctrl_d1;
reg [SLAVE_NUM-1:0]bus2_sel_ctrl_d1;
reg [SLAVE_NUM-1:0]bus3_sel_ctrl_d1;
reg [SLAVE_NUM-1:0]bus4_sel_ctrl_d1;
always @(posedge clk_sys or negedge rst_n_sys) begin
    if(~rst_n_sys)begin
        bus1_sel_ctrl_d1 <= 'h0;
        bus2_sel_ctrl_d1 <= 'h0;
        bus3_sel_ctrl_d1 <= 'h0;
        bus4_sel_ctrl_d1 <= 'h0;
    end else begin
        bus1_sel_ctrl_d1 <= bus1_sel_ctrl;
        bus2_sel_ctrl_d1 <= bus2_sel_ctrl;
        bus3_sel_ctrl_d1 <= bus3_sel_ctrl;
        bus4_sel_ctrl_d1 <= bus4_sel_ctrl;
    end
end
wire [SLAVE_NUM*2+1:0]bus1_ctrl_tmp;
wire [SLAVE_NUM*2-1:0]bus2_ctrl_tmp;
wire [SLAVE_NUM*2-1:0]bus3_ctrl_tmp;
wire [SLAVE_NUM*2-1:0]bus4_ctrl_tmp;


// assign bus1_ctrl_tmp[75] = bus1_sel_ctrl_d1[37] && np_wr_d2;
// assign bus1_ctrl_tmp[74] = bus1_sel_ctrl_d1[37] && np_rd_d2;
// assign bus1_ctrl_tmp[73] = bus1_sel_ctrl_d1[36] && np_wr_d2;
// assign bus1_ctrl_tmp[72] = bus1_sel_ctrl_d1[36] && np_rd_d2;
// assign bus1_ctrl_tmp[71] = bus1_sel_ctrl_d1[35] && np_wr_d2;
// assign bus1_ctrl_tmp[70] = bus1_sel_ctrl_d1[35] && np_rd_d2;
// assign bus1_ctrl_tmp[69] = bus1_sel_ctrl_d1[34] && np_wr_d2;
// assign bus1_ctrl_tmp[68] = bus1_sel_ctrl_d1[34] && np_rd_d2;
// assign bus1_ctrl_tmp[67] = bus1_sel_ctrl_d1[33] && np_wr_d2;
// assign bus1_ctrl_tmp[66] = bus1_sel_ctrl_d1[33] && np_rd_d2;
// assign bus1_ctrl_tmp[65] = bus1_sel_ctrl_d1[32] && np_wr_d2;
// assign bus1_ctrl_tmp[64] = bus1_sel_ctrl_d1[32] && np_rd_d2;
// assign bus1_ctrl_tmp[63] = bus1_sel_ctrl_d1[31] && np_wr_d2;
// assign bus1_ctrl_tmp[62] = bus1_sel_ctrl_d1[31] && np_rd_d2;
// assign bus1_ctrl_tmp[61] = bus1_sel_ctrl_d1[30] && np_wr_d2;
// assign bus1_ctrl_tmp[60] = bus1_sel_ctrl_d1[30] && np_rd_d2;
// assign bus1_ctrl_tmp[59] = bus1_sel_ctrl_d1[29] && np_wr_d2;
// assign bus1_ctrl_tmp[58] = bus1_sel_ctrl_d1[29] && np_rd_d2;
// assign bus1_ctrl_tmp[57] = bus1_sel_ctrl_d1[28] && np_wr_d2;
// assign bus1_ctrl_tmp[56] = bus1_sel_ctrl_d1[28] && np_rd_d2;
// assign bus1_ctrl_tmp[55] = bus1_sel_ctrl_d1[27] && np_wr_d2;
// assign bus1_ctrl_tmp[54] = bus1_sel_ctrl_d1[27] && np_rd_d2;
assign bus1_ctrl_tmp[53] = bus1_sel_ctrl_d1[26] && np_wr_d2;
assign bus1_ctrl_tmp[52] = bus1_sel_ctrl_d1[26] && np_rd_d2;
assign bus1_ctrl_tmp[51] = bus1_sel_ctrl_d1[25] && np_wr_d2;
assign bus1_ctrl_tmp[50] = bus1_sel_ctrl_d1[25] && np_rd_d2;
assign bus1_ctrl_tmp[49] = bus1_sel_ctrl_d1[24] && np_wr_d2;
assign bus1_ctrl_tmp[48] = bus1_sel_ctrl_d1[24] && np_rd_d2;
assign bus1_ctrl_tmp[47] = bus1_sel_ctrl_d1[23] && np_wr_d2;
assign bus1_ctrl_tmp[46] = bus1_sel_ctrl_d1[23] && np_rd_d2;
assign bus1_ctrl_tmp[45] = bus1_sel_ctrl_d1[22] && np_wr_d2;
assign bus1_ctrl_tmp[44] = bus1_sel_ctrl_d1[22] && np_rd_d2;
assign bus1_ctrl_tmp[43] = bus1_sel_ctrl_d1[21] && np_wr_d2;
assign bus1_ctrl_tmp[42] = bus1_sel_ctrl_d1[21] && np_rd_d2;
assign bus1_ctrl_tmp[41] = bus1_sel_ctrl_d1[20] && np_wr_d2;
assign bus1_ctrl_tmp[40] = bus1_sel_ctrl_d1[20] && np_rd_d2;
assign bus1_ctrl_tmp[39] = bus1_sel_ctrl_d1[19] && np_wr_d2;
assign bus1_ctrl_tmp[38] = bus1_sel_ctrl_d1[19] && np_rd_d2;
assign bus1_ctrl_tmp[37] = bus1_sel_ctrl_d1[18] && np_wr_d2;
assign bus1_ctrl_tmp[36] = bus1_sel_ctrl_d1[18] && np_rd_d2;
assign bus1_ctrl_tmp[35] = bus1_sel_ctrl_d1[17] && np_wr_d2;
assign bus1_ctrl_tmp[34] = bus1_sel_ctrl_d1[17] && np_rd_d2;
assign bus1_ctrl_tmp[33] = bus1_sel_ctrl_d1[16] && np_wr_d2;
assign bus1_ctrl_tmp[32] = bus1_sel_ctrl_d1[16] && np_rd_d2;
assign bus1_ctrl_tmp[31] = bus1_sel_ctrl_d1[15] && np_wr_d2;
assign bus1_ctrl_tmp[30] = bus1_sel_ctrl_d1[15] && np_rd_d2;
assign bus1_ctrl_tmp[29] = bus1_sel_ctrl_d1[14] && np_wr_d2;
assign bus1_ctrl_tmp[28] = bus1_sel_ctrl_d1[14] && np_rd_d2;
assign bus1_ctrl_tmp[27] = bus1_sel_ctrl_d1[13] && np_wr_d2;
assign bus1_ctrl_tmp[26] = bus1_sel_ctrl_d1[13] && np_rd_d2;
assign bus1_ctrl_tmp[25] = bus1_sel_ctrl_d1[12] && np_wr_d2;
assign bus1_ctrl_tmp[24] = bus1_sel_ctrl_d1[12] && np_rd_d2;
assign bus1_ctrl_tmp[23] = bus1_sel_ctrl_d1[11] && np_wr_d2;
assign bus1_ctrl_tmp[22] = bus1_sel_ctrl_d1[11] && np_rd_d2;
assign bus1_ctrl_tmp[21] = bus1_sel_ctrl_d1[10] && np_wr_d2;
assign bus1_ctrl_tmp[20] = bus1_sel_ctrl_d1[10] && np_rd_d2;
assign bus1_ctrl_tmp[19] = bus1_sel_ctrl_d1[ 9] && np_wr_d2;
assign bus1_ctrl_tmp[18] = bus1_sel_ctrl_d1[ 9] && np_rd_d2;
assign bus1_ctrl_tmp[17] = bus1_sel_ctrl_d1[ 8] && np_wr_d2;
assign bus1_ctrl_tmp[16] = bus1_sel_ctrl_d1[ 8] && np_rd_d2;
assign bus1_ctrl_tmp[15] = bus1_sel_ctrl_d1[ 7] && np_wr_d2;
assign bus1_ctrl_tmp[14] = bus1_sel_ctrl_d1[ 7] && np_rd_d2;
assign bus1_ctrl_tmp[13] = bus1_sel_ctrl_d1[ 6] && np_wr_d2;
assign bus1_ctrl_tmp[12] = bus1_sel_ctrl_d1[ 6] && np_rd_d2;
assign bus1_ctrl_tmp[11] = bus1_sel_ctrl_d1[ 5] && np_wr_d2;
assign bus1_ctrl_tmp[10] = bus1_sel_ctrl_d1[ 5] && np_rd_d2;
assign bus1_ctrl_tmp[ 9] = bus1_sel_ctrl_d1[ 4] && np_wr_d2;
assign bus1_ctrl_tmp[ 8] = bus1_sel_ctrl_d1[ 4] && np_rd_d2;
assign bus1_ctrl_tmp[ 7] = bus1_sel_ctrl_d1[ 3] && np_wr_d2;
assign bus1_ctrl_tmp[ 6] = bus1_sel_ctrl_d1[ 3] && np_rd_d2;
assign bus1_ctrl_tmp[ 5] = bus1_sel_ctrl_d1[ 2] && np_wr_d2;
assign bus1_ctrl_tmp[ 4] = bus1_sel_ctrl_d1[ 2] && np_rd_d2;
assign bus1_ctrl_tmp[ 3] = bus1_sel_ctrl_d1[ 1] && np_wr_d2;
assign bus1_ctrl_tmp[ 2] = bus1_sel_ctrl_d1[ 1] && np_rd_d2;
assign bus1_ctrl_tmp[ 1] = bus1_sel_ctrl_d1[ 0] && np_wr_d2;
assign bus1_ctrl_tmp[ 0] = bus1_sel_ctrl_d1[ 0] && np_rd_d2;



// assign bus2_ctrl_tmp[75] = bus2_sel_ctrl_d1[37] && np_wr_d2;
// assign bus2_ctrl_tmp[74] = bus2_sel_ctrl_d1[37] && np_rd_d2;
// assign bus2_ctrl_tmp[73] = bus2_sel_ctrl_d1[36] && np_wr_d2;
// assign bus2_ctrl_tmp[72] = bus2_sel_ctrl_d1[36] && np_rd_d2;
// assign bus2_ctrl_tmp[71] = bus2_sel_ctrl_d1[35] && np_wr_d2;
// assign bus2_ctrl_tmp[70] = bus2_sel_ctrl_d1[35] && np_rd_d2;
// assign bus2_ctrl_tmp[69] = bus2_sel_ctrl_d1[34] && np_wr_d2;
// assign bus2_ctrl_tmp[68] = bus2_sel_ctrl_d1[34] && np_rd_d2;
// assign bus2_ctrl_tmp[67] = bus2_sel_ctrl_d1[33] && np_wr_d2;
// assign bus2_ctrl_tmp[66] = bus2_sel_ctrl_d1[33] && np_rd_d2;
// assign bus2_ctrl_tmp[65] = bus2_sel_ctrl_d1[32] && np_wr_d2;
// assign bus2_ctrl_tmp[64] = bus2_sel_ctrl_d1[32] && np_rd_d2;
// assign bus2_ctrl_tmp[63] = bus2_sel_ctrl_d1[31] && np_wr_d2;
// assign bus2_ctrl_tmp[62] = bus2_sel_ctrl_d1[31] && np_rd_d2;
// assign bus2_ctrl_tmp[61] = bus2_sel_ctrl_d1[30] && np_wr_d2;
// assign bus2_ctrl_tmp[60] = bus2_sel_ctrl_d1[30] && np_rd_d2;
// assign bus2_ctrl_tmp[59] = bus2_sel_ctrl_d1[29] && np_wr_d2;
// assign bus2_ctrl_tmp[58] = bus2_sel_ctrl_d1[29] && np_rd_d2;
// assign bus2_ctrl_tmp[57] = bus2_sel_ctrl_d1[28] && np_wr_d2;
// assign bus2_ctrl_tmp[56] = bus2_sel_ctrl_d1[28] && np_rd_d2;
// assign bus2_ctrl_tmp[55] = bus2_sel_ctrl_d1[27] && np_wr_d2;
// assign bus2_ctrl_tmp[54] = bus2_sel_ctrl_d1[27] && np_rd_d2;
// assign bus2_ctrl_tmp[53] = bus2_sel_ctrl_d1[26] && np_wr_d2;
// assign bus2_ctrl_tmp[52] = bus2_sel_ctrl_d1[26] && np_rd_d2;
assign bus2_ctrl_tmp[51] = bus2_sel_ctrl_d1[25] && np_wr_d2;
assign bus2_ctrl_tmp[50] = bus2_sel_ctrl_d1[25] && np_rd_d2;
assign bus2_ctrl_tmp[49] = bus2_sel_ctrl_d1[24] && np_wr_d2;
assign bus2_ctrl_tmp[48] = bus2_sel_ctrl_d1[24] && np_rd_d2;
assign bus2_ctrl_tmp[47] = bus2_sel_ctrl_d1[23] && np_wr_d2;
assign bus2_ctrl_tmp[46] = bus2_sel_ctrl_d1[23] && np_rd_d2;
assign bus2_ctrl_tmp[45] = bus2_sel_ctrl_d1[22] && np_wr_d2;
assign bus2_ctrl_tmp[44] = bus2_sel_ctrl_d1[22] && np_rd_d2;
assign bus2_ctrl_tmp[43] = bus2_sel_ctrl_d1[21] && np_wr_d2;
assign bus2_ctrl_tmp[42] = bus2_sel_ctrl_d1[21] && np_rd_d2;
assign bus2_ctrl_tmp[41] = bus2_sel_ctrl_d1[20] && np_wr_d2;
assign bus2_ctrl_tmp[40] = bus2_sel_ctrl_d1[20] && np_rd_d2;
assign bus2_ctrl_tmp[39] = bus2_sel_ctrl_d1[19] && np_wr_d2;
assign bus2_ctrl_tmp[38] = bus2_sel_ctrl_d1[19] && np_rd_d2;
assign bus2_ctrl_tmp[37] = bus2_sel_ctrl_d1[18] && np_wr_d2;
assign bus2_ctrl_tmp[36] = bus2_sel_ctrl_d1[18] && np_rd_d2;
assign bus2_ctrl_tmp[35] = bus2_sel_ctrl_d1[17] && np_wr_d2;
assign bus2_ctrl_tmp[34] = bus2_sel_ctrl_d1[17] && np_rd_d2;
assign bus2_ctrl_tmp[33] = bus2_sel_ctrl_d1[16] && np_wr_d2;
assign bus2_ctrl_tmp[32] = bus2_sel_ctrl_d1[16] && np_rd_d2;
assign bus2_ctrl_tmp[31] = bus2_sel_ctrl_d1[15] && np_wr_d2;
assign bus2_ctrl_tmp[30] = bus2_sel_ctrl_d1[15] && np_rd_d2;
assign bus2_ctrl_tmp[29] = bus2_sel_ctrl_d1[14] && np_wr_d2;
assign bus2_ctrl_tmp[28] = bus2_sel_ctrl_d1[14] && np_rd_d2;
assign bus2_ctrl_tmp[27] = bus2_sel_ctrl_d1[13] && np_wr_d2;
assign bus2_ctrl_tmp[26] = bus2_sel_ctrl_d1[13] && np_rd_d2;
assign bus2_ctrl_tmp[25] = bus2_sel_ctrl_d1[12] && np_wr_d2;
assign bus2_ctrl_tmp[24] = bus2_sel_ctrl_d1[12] && np_rd_d2;
assign bus2_ctrl_tmp[23] = bus2_sel_ctrl_d1[11] && np_wr_d2;
assign bus2_ctrl_tmp[22] = bus2_sel_ctrl_d1[11] && np_rd_d2;
assign bus2_ctrl_tmp[21] = bus2_sel_ctrl_d1[10] && np_wr_d2;
assign bus2_ctrl_tmp[20] = bus2_sel_ctrl_d1[10] && np_rd_d2;
assign bus2_ctrl_tmp[19] = bus2_sel_ctrl_d1[ 9] && np_wr_d2;
assign bus2_ctrl_tmp[18] = bus2_sel_ctrl_d1[ 9] && np_rd_d2;
assign bus2_ctrl_tmp[17] = bus2_sel_ctrl_d1[ 8] && np_wr_d2;
assign bus2_ctrl_tmp[16] = bus2_sel_ctrl_d1[ 8] && np_rd_d2;
assign bus2_ctrl_tmp[15] = bus2_sel_ctrl_d1[ 7] && np_wr_d2;
assign bus2_ctrl_tmp[14] = bus2_sel_ctrl_d1[ 7] && np_rd_d2;
assign bus2_ctrl_tmp[13] = bus2_sel_ctrl_d1[ 6] && np_wr_d2;
assign bus2_ctrl_tmp[12] = bus2_sel_ctrl_d1[ 6] && np_rd_d2;
assign bus2_ctrl_tmp[11] = bus2_sel_ctrl_d1[ 5] && np_wr_d2;
assign bus2_ctrl_tmp[10] = bus2_sel_ctrl_d1[ 5] && np_rd_d2;
assign bus2_ctrl_tmp[ 9] = bus2_sel_ctrl_d1[ 4] && np_wr_d2;
assign bus2_ctrl_tmp[ 8] = bus2_sel_ctrl_d1[ 4] && np_rd_d2;
assign bus2_ctrl_tmp[ 7] = bus2_sel_ctrl_d1[ 3] && np_wr_d2;
assign bus2_ctrl_tmp[ 6] = bus2_sel_ctrl_d1[ 3] && np_rd_d2;
assign bus2_ctrl_tmp[ 5] = bus2_sel_ctrl_d1[ 2] && np_wr_d2;
assign bus2_ctrl_tmp[ 4] = bus2_sel_ctrl_d1[ 2] && np_rd_d2;
assign bus2_ctrl_tmp[ 3] = bus2_sel_ctrl_d1[ 1] && np_wr_d2;
assign bus2_ctrl_tmp[ 2] = bus2_sel_ctrl_d1[ 1] && np_rd_d2;
assign bus2_ctrl_tmp[ 1] = bus2_sel_ctrl_d1[ 0] && np_wr_d2;
assign bus2_ctrl_tmp[ 0] = bus2_sel_ctrl_d1[ 0] && np_rd_d2;



// assign bus3_ctrl_tmp[75] = bus3_sel_ctrl_d1[37] && np_wr_d2;
// assign bus3_ctrl_tmp[74] = bus3_sel_ctrl_d1[37] && np_rd_d2;
// assign bus3_ctrl_tmp[73] = bus3_sel_ctrl_d1[36] && np_wr_d2;
// assign bus3_ctrl_tmp[72] = bus3_sel_ctrl_d1[36] && np_rd_d2;
// assign bus3_ctrl_tmp[71] = bus3_sel_ctrl_d1[35] && np_wr_d2;
// assign bus3_ctrl_tmp[70] = bus3_sel_ctrl_d1[35] && np_rd_d2;
// assign bus3_ctrl_tmp[69] = bus3_sel_ctrl_d1[34] && np_wr_d2;
// assign bus3_ctrl_tmp[68] = bus3_sel_ctrl_d1[34] && np_rd_d2;
// assign bus3_ctrl_tmp[67] = bus3_sel_ctrl_d1[33] && np_wr_d2;
// assign bus3_ctrl_tmp[66] = bus3_sel_ctrl_d1[33] && np_rd_d2;
// assign bus3_ctrl_tmp[65] = bus3_sel_ctrl_d1[32] && np_wr_d2;
// assign bus3_ctrl_tmp[64] = bus3_sel_ctrl_d1[32] && np_rd_d2;
// assign bus3_ctrl_tmp[63] = bus3_sel_ctrl_d1[31] && np_wr_d2;
// assign bus3_ctrl_tmp[62] = bus3_sel_ctrl_d1[31] && np_rd_d2;
// assign bus3_ctrl_tmp[61] = bus3_sel_ctrl_d1[30] && np_wr_d2;
// assign bus3_ctrl_tmp[60] = bus3_sel_ctrl_d1[30] && np_rd_d2;
// assign bus3_ctrl_tmp[59] = bus3_sel_ctrl_d1[29] && np_wr_d2;
// assign bus3_ctrl_tmp[58] = bus3_sel_ctrl_d1[29] && np_rd_d2;
// assign bus3_ctrl_tmp[57] = bus3_sel_ctrl_d1[28] && np_wr_d2;
// assign bus3_ctrl_tmp[56] = bus3_sel_ctrl_d1[28] && np_rd_d2;
// assign bus3_ctrl_tmp[55] = bus3_sel_ctrl_d1[27] && np_wr_d2;
// assign bus3_ctrl_tmp[54] = bus3_sel_ctrl_d1[27] && np_rd_d2;
// assign bus3_ctrl_tmp[53] = bus3_sel_ctrl_d1[26] && np_wr_d2;
// assign bus3_ctrl_tmp[52] = bus3_sel_ctrl_d1[26] && np_rd_d2;
assign bus3_ctrl_tmp[51] = bus3_sel_ctrl_d1[25] && np_wr_d2;
assign bus3_ctrl_tmp[50] = bus3_sel_ctrl_d1[25] && np_rd_d2;
assign bus3_ctrl_tmp[49] = bus3_sel_ctrl_d1[24] && np_wr_d2;
assign bus3_ctrl_tmp[48] = bus3_sel_ctrl_d1[24] && np_rd_d2;
assign bus3_ctrl_tmp[47] = bus3_sel_ctrl_d1[23] && np_wr_d2;
assign bus3_ctrl_tmp[46] = bus3_sel_ctrl_d1[23] && np_rd_d2;
assign bus3_ctrl_tmp[45] = bus3_sel_ctrl_d1[22] && np_wr_d2;
assign bus3_ctrl_tmp[44] = bus3_sel_ctrl_d1[22] && np_rd_d2;
assign bus3_ctrl_tmp[43] = bus3_sel_ctrl_d1[21] && np_wr_d2;
assign bus3_ctrl_tmp[42] = bus3_sel_ctrl_d1[21] && np_rd_d2;
assign bus3_ctrl_tmp[41] = bus3_sel_ctrl_d1[20] && np_wr_d2;
assign bus3_ctrl_tmp[40] = bus3_sel_ctrl_d1[20] && np_rd_d2;
assign bus3_ctrl_tmp[39] = bus3_sel_ctrl_d1[19] && np_wr_d2;
assign bus3_ctrl_tmp[38] = bus3_sel_ctrl_d1[19] && np_rd_d2;
assign bus3_ctrl_tmp[37] = bus3_sel_ctrl_d1[18] && np_wr_d2;
assign bus3_ctrl_tmp[36] = bus3_sel_ctrl_d1[18] && np_rd_d2;
assign bus3_ctrl_tmp[35] = bus3_sel_ctrl_d1[17] && np_wr_d2;
assign bus3_ctrl_tmp[34] = bus3_sel_ctrl_d1[17] && np_rd_d2;
assign bus3_ctrl_tmp[33] = bus3_sel_ctrl_d1[16] && np_wr_d2;
assign bus3_ctrl_tmp[32] = bus3_sel_ctrl_d1[16] && np_rd_d2;
assign bus3_ctrl_tmp[31] = bus3_sel_ctrl_d1[15] && np_wr_d2;
assign bus3_ctrl_tmp[30] = bus3_sel_ctrl_d1[15] && np_rd_d2;
assign bus3_ctrl_tmp[29] = bus3_sel_ctrl_d1[14] && np_wr_d2;
assign bus3_ctrl_tmp[28] = bus3_sel_ctrl_d1[14] && np_rd_d2;
assign bus3_ctrl_tmp[27] = bus3_sel_ctrl_d1[13] && np_wr_d2;
assign bus3_ctrl_tmp[26] = bus3_sel_ctrl_d1[13] && np_rd_d2;
assign bus3_ctrl_tmp[25] = bus3_sel_ctrl_d1[12] && np_wr_d2;
assign bus3_ctrl_tmp[24] = bus3_sel_ctrl_d1[12] && np_rd_d2;
assign bus3_ctrl_tmp[23] = bus3_sel_ctrl_d1[11] && np_wr_d2;
assign bus3_ctrl_tmp[22] = bus3_sel_ctrl_d1[11] && np_rd_d2;
assign bus3_ctrl_tmp[21] = bus3_sel_ctrl_d1[10] && np_wr_d2;
assign bus3_ctrl_tmp[20] = bus3_sel_ctrl_d1[10] && np_rd_d2;
assign bus3_ctrl_tmp[19] = bus3_sel_ctrl_d1[ 9] && np_wr_d2;
assign bus3_ctrl_tmp[18] = bus3_sel_ctrl_d1[ 9] && np_rd_d2;
assign bus3_ctrl_tmp[17] = bus3_sel_ctrl_d1[ 8] && np_wr_d2;
assign bus3_ctrl_tmp[16] = bus3_sel_ctrl_d1[ 8] && np_rd_d2;
assign bus3_ctrl_tmp[15] = bus3_sel_ctrl_d1[ 7] && np_wr_d2;
assign bus3_ctrl_tmp[14] = bus3_sel_ctrl_d1[ 7] && np_rd_d2;
assign bus3_ctrl_tmp[13] = bus3_sel_ctrl_d1[ 6] && np_wr_d2;
assign bus3_ctrl_tmp[12] = bus3_sel_ctrl_d1[ 6] && np_rd_d2;
assign bus3_ctrl_tmp[11] = bus3_sel_ctrl_d1[ 5] && np_wr_d2;
assign bus3_ctrl_tmp[10] = bus3_sel_ctrl_d1[ 5] && np_rd_d2;
assign bus3_ctrl_tmp[ 9] = bus3_sel_ctrl_d1[ 4] && np_wr_d2;
assign bus3_ctrl_tmp[ 8] = bus3_sel_ctrl_d1[ 4] && np_rd_d2;
assign bus3_ctrl_tmp[ 7] = bus3_sel_ctrl_d1[ 3] && np_wr_d2;
assign bus3_ctrl_tmp[ 6] = bus3_sel_ctrl_d1[ 3] && np_rd_d2;
assign bus3_ctrl_tmp[ 5] = bus3_sel_ctrl_d1[ 2] && np_wr_d2;
assign bus3_ctrl_tmp[ 4] = bus3_sel_ctrl_d1[ 2] && np_rd_d2;
assign bus3_ctrl_tmp[ 3] = bus3_sel_ctrl_d1[ 1] && np_wr_d2;
assign bus3_ctrl_tmp[ 2] = bus3_sel_ctrl_d1[ 1] && np_rd_d2;
assign bus3_ctrl_tmp[ 1] = bus3_sel_ctrl_d1[ 0] && np_wr_d2;
assign bus3_ctrl_tmp[ 0] = bus3_sel_ctrl_d1[ 0] && np_rd_d2;



// assign bus4_ctrl_tmp[75] = bus4_sel_ctrl_d1[37] && np_wr_d2;
// assign bus4_ctrl_tmp[74] = bus4_sel_ctrl_d1[37] && np_rd_d2;
// assign bus4_ctrl_tmp[73] = bus4_sel_ctrl_d1[36] && np_wr_d2;
// assign bus4_ctrl_tmp[72] = bus4_sel_ctrl_d1[36] && np_rd_d2;
// assign bus4_ctrl_tmp[71] = bus4_sel_ctrl_d1[35] && np_wr_d2;
// assign bus4_ctrl_tmp[70] = bus4_sel_ctrl_d1[35] && np_rd_d2;
// assign bus4_ctrl_tmp[69] = bus4_sel_ctrl_d1[34] && np_wr_d2;
// assign bus4_ctrl_tmp[68] = bus4_sel_ctrl_d1[34] && np_rd_d2;
// assign bus4_ctrl_tmp[67] = bus4_sel_ctrl_d1[33] && np_wr_d2;
// assign bus4_ctrl_tmp[66] = bus4_sel_ctrl_d1[33] && np_rd_d2;
// assign bus4_ctrl_tmp[65] = bus4_sel_ctrl_d1[32] && np_wr_d2;
// assign bus4_ctrl_tmp[64] = bus4_sel_ctrl_d1[32] && np_rd_d2;
// assign bus4_ctrl_tmp[63] = bus4_sel_ctrl_d1[31] && np_wr_d2;
// assign bus4_ctrl_tmp[62] = bus4_sel_ctrl_d1[31] && np_rd_d2;
// assign bus4_ctrl_tmp[61] = bus4_sel_ctrl_d1[30] && np_wr_d2;
// assign bus4_ctrl_tmp[60] = bus4_sel_ctrl_d1[30] && np_rd_d2;
// assign bus4_ctrl_tmp[59] = bus4_sel_ctrl_d1[29] && np_wr_d2;
// assign bus4_ctrl_tmp[58] = bus4_sel_ctrl_d1[29] && np_rd_d2;
// assign bus4_ctrl_tmp[57] = bus4_sel_ctrl_d1[28] && np_wr_d2;
// assign bus4_ctrl_tmp[56] = bus4_sel_ctrl_d1[28] && np_rd_d2;
// assign bus4_ctrl_tmp[55] = bus4_sel_ctrl_d1[27] && np_wr_d2;
// assign bus4_ctrl_tmp[54] = bus4_sel_ctrl_d1[27] && np_rd_d2;
// assign bus4_ctrl_tmp[53] = bus4_sel_ctrl_d1[26] && np_wr_d2;
// assign bus4_ctrl_tmp[52] = bus4_sel_ctrl_d1[26] && np_rd_d2;
assign bus4_ctrl_tmp[51] = bus4_sel_ctrl_d1[25] && np_wr_d2;
assign bus4_ctrl_tmp[50] = bus4_sel_ctrl_d1[25] && np_rd_d2;
assign bus4_ctrl_tmp[49] = bus4_sel_ctrl_d1[24] && np_wr_d2;
assign bus4_ctrl_tmp[48] = bus4_sel_ctrl_d1[24] && np_rd_d2;
assign bus4_ctrl_tmp[47] = bus4_sel_ctrl_d1[23] && np_wr_d2;
assign bus4_ctrl_tmp[46] = bus4_sel_ctrl_d1[23] && np_rd_d2;
assign bus4_ctrl_tmp[45] = bus4_sel_ctrl_d1[22] && np_wr_d2;
assign bus4_ctrl_tmp[44] = bus4_sel_ctrl_d1[22] && np_rd_d2;
assign bus4_ctrl_tmp[43] = bus4_sel_ctrl_d1[21] && np_wr_d2;
assign bus4_ctrl_tmp[42] = bus4_sel_ctrl_d1[21] && np_rd_d2;
assign bus4_ctrl_tmp[41] = bus4_sel_ctrl_d1[20] && np_wr_d2;
assign bus4_ctrl_tmp[40] = bus4_sel_ctrl_d1[20] && np_rd_d2;
assign bus4_ctrl_tmp[39] = bus4_sel_ctrl_d1[19] && np_wr_d2;
assign bus4_ctrl_tmp[38] = bus4_sel_ctrl_d1[19] && np_rd_d2;
assign bus4_ctrl_tmp[37] = bus4_sel_ctrl_d1[18] && np_wr_d2;
assign bus4_ctrl_tmp[36] = bus4_sel_ctrl_d1[18] && np_rd_d2;
assign bus4_ctrl_tmp[35] = bus4_sel_ctrl_d1[17] && np_wr_d2;
assign bus4_ctrl_tmp[34] = bus4_sel_ctrl_d1[17] && np_rd_d2;
assign bus4_ctrl_tmp[33] = bus4_sel_ctrl_d1[16] && np_wr_d2;
assign bus4_ctrl_tmp[32] = bus4_sel_ctrl_d1[16] && np_rd_d2;
assign bus4_ctrl_tmp[31] = bus4_sel_ctrl_d1[15] && np_wr_d2;
assign bus4_ctrl_tmp[30] = bus4_sel_ctrl_d1[15] && np_rd_d2;
assign bus4_ctrl_tmp[29] = bus4_sel_ctrl_d1[14] && np_wr_d2;
assign bus4_ctrl_tmp[28] = bus4_sel_ctrl_d1[14] && np_rd_d2;
assign bus4_ctrl_tmp[27] = bus4_sel_ctrl_d1[13] && np_wr_d2;
assign bus4_ctrl_tmp[26] = bus4_sel_ctrl_d1[13] && np_rd_d2;
assign bus4_ctrl_tmp[25] = bus4_sel_ctrl_d1[12] && np_wr_d2;
assign bus4_ctrl_tmp[24] = bus4_sel_ctrl_d1[12] && np_rd_d2;
assign bus4_ctrl_tmp[23] = bus4_sel_ctrl_d1[11] && np_wr_d2;
assign bus4_ctrl_tmp[22] = bus4_sel_ctrl_d1[11] && np_rd_d2;
assign bus4_ctrl_tmp[21] = bus4_sel_ctrl_d1[10] && np_wr_d2;
assign bus4_ctrl_tmp[20] = bus4_sel_ctrl_d1[10] && np_rd_d2;
assign bus4_ctrl_tmp[19] = bus4_sel_ctrl_d1[ 9] && np_wr_d2;
assign bus4_ctrl_tmp[18] = bus4_sel_ctrl_d1[ 9] && np_rd_d2;
assign bus4_ctrl_tmp[17] = bus4_sel_ctrl_d1[ 8] && np_wr_d2;
assign bus4_ctrl_tmp[16] = bus4_sel_ctrl_d1[ 8] && np_rd_d2;
assign bus4_ctrl_tmp[15] = bus4_sel_ctrl_d1[ 7] && np_wr_d2;
assign bus4_ctrl_tmp[14] = bus4_sel_ctrl_d1[ 7] && np_rd_d2;
assign bus4_ctrl_tmp[13] = bus4_sel_ctrl_d1[ 6] && np_wr_d2;
assign bus4_ctrl_tmp[12] = bus4_sel_ctrl_d1[ 6] && np_rd_d2;
assign bus4_ctrl_tmp[11] = bus4_sel_ctrl_d1[ 5] && np_wr_d2;
assign bus4_ctrl_tmp[10] = bus4_sel_ctrl_d1[ 5] && np_rd_d2;
assign bus4_ctrl_tmp[ 9] = bus4_sel_ctrl_d1[ 4] && np_wr_d2;
assign bus4_ctrl_tmp[ 8] = bus4_sel_ctrl_d1[ 4] && np_rd_d2;
assign bus4_ctrl_tmp[ 7] = bus4_sel_ctrl_d1[ 3] && np_wr_d2;
assign bus4_ctrl_tmp[ 6] = bus4_sel_ctrl_d1[ 3] && np_rd_d2;
assign bus4_ctrl_tmp[ 5] = bus4_sel_ctrl_d1[ 2] && np_wr_d2;
assign bus4_ctrl_tmp[ 4] = bus4_sel_ctrl_d1[ 2] && np_rd_d2;
assign bus4_ctrl_tmp[ 3] = bus4_sel_ctrl_d1[ 1] && np_wr_d2;
assign bus4_ctrl_tmp[ 2] = bus4_sel_ctrl_d1[ 1] && np_rd_d2;
assign bus4_ctrl_tmp[ 1] = bus4_sel_ctrl_d1[ 0] && np_wr_d2;
assign bus4_ctrl_tmp[ 0] = bus4_sel_ctrl_d1[ 0] && np_rd_d2;
assign bus1_np_addr_ctrl = bus1_ctrl_tmp;
assign bus2_np_addr_ctrl = bus2_ctrl_tmp;
assign bus3_np_addr_ctrl = bus3_ctrl_tmp;
assign bus4_np_addr_ctrl = bus4_ctrl_tmp;

endmodule


